Energy Efficient Non Volatile Cache Memory Design Using Asymmetric Encoding

With the surge in data-intensive applications over the years, today's computing systems need to handle large amounts of data, necessitating large caches in such systems. Emerging devices based on technologies such as FeRAM, FeFET, and STTRAM possess Multi-Level Cell (MLC) storage capabilities and are utilized to design dense storage to address this need. Recent works have shown that FeRAM exhibits properties such as scalable low-voltage operation and good endurance, making it a suitable candidate for last level caches (LLCs). This paper leverages FeRAM's multi-state storage capabilities to propose a novel encoding scheme for cache applications. We propose a dynamic frequency based asymmetric coding (DFBAC) which utilizes asymmetric (variable) length pattern encoding combined with energy-aware MLC state mapping. The asymmetric length encodes multiple bits of information into a single MLC state. This inherently performs hardware data compression. As a result, it reduces the number of cell writes and reads, which lowers the overall energy consumption during cache operations. Our benchmark evaluations shows that the proposed scheme reduces energy consumption on overall data access by upto 41.79% and 74.43% compared to 2 bit MLC baseline cache as well as 30.69% and 74.16% compared to the state-of-the-art in L1 and L2 cache respectively.